The present invention relates to a clock phase acquisition/tracking device and a method for phase acquisition for being appropriately used, for instance, to read data in magnetic recording devices or to regenerate received signals in communication devices.
In recent years, PRML (Partial Response Maximum Likelihood) method combining partial response and maximum likelihood detection is generally used for recording/regenerating method of a magnetic disk drive as a magnetic recording device for recording data using magnetic property on the disk. Namely, it is known that this PRML method is a signal processing technology indispensable for high-density recording of data on the disk.
FIG. 24 shows the composition of a data read section 100 of a magnetic disk drive to which the PRML method is applied. As shown in this FIG. 24, the amplitude of the (electric) signal regenerated by a head 101 is amplified by a preamplifier 102 or an AGC (Automatic Gain Control) 103.
Then, in the data read section 100, a signal from the AGC 103 is equalized to a constant signal presenting partial response by an equalizer such as pre-filter 104 or FIR (Finite Impulse Response) filter 106, and "0" or "1" of the signal is discriminated by a maximum likelihood detector 111.
Now, the pre-filter 104 is an analog filter as a signal processing circuit of continuous time, while the FIR filter 106 is a digital filter as a signal processing circuit of discrete time. An analog/digital converter (ADC) 105 for converting an analog signal into a digital signal is interposed between the pre-filter 104 and FIR filter 106. In other words, this ADC 105 quantizes signals from the pre-filter 104.
When the downstream section after the FIR filter 106 is a continuous time signal processing circuit (analog circuit), a sample holder for holding sampled data for a certain time is interposed as a quantization circuit.
In the ADC 105, an analog signal is converted into a digital signal based on a clock, and the phase of this clock is so adjusted that the quantization can be realized at a given timing from the output of the FIR filter circuit 106 by a PLL (Phase Locked Loop) circuit 112.
By this composition, in the PLL circuit 112, a phase error computation circuit 107 computes the phase error E.sub..tau. (phase error between clock phase generated by a VCO 110 and desired quantization timing) from the signal equalized by the FIR filter 106 (digital signal; y.sub.n).
The phase error E.sub..tau. computed by the phase error computation circuit 107 is converted into an analog signal by a D/A converter (DAC) 108 and output, through a loop filter 109, to the voltage control oscillator (VCO) 110 for generating a clock signal.
The VCO 110 generates a clock signal using the phase error information E.sub..tau. from the loop filter 109 as control signal and the A/D conversion procession in the A/D converter 105 is executed based on this clock timing.
In other words, acquisition and tracking of the clock phase input as quantization timing in the A/D converter 105 can be achieved through the feedback, by the PLL circuit 112, from signal A/D-converted by the A/D converter 105.
Here, the clock phase acquisition mentioned above indicates a state wherein the PLL circuit 112 operates so that the phase error E.sub..tau. can be stable around 0 when this phase error E.sub..tau. computed by the phase error computation circuit 107 is unstable around 0. While clock phase tracking indicates a state wherein the phase error E.sub..tau. computed by the phase error computation circuit 107 is stable around 0 and the PLL circuit 112 operates so that the phase error E.sub..tau. remains around 0 thereafter.
When the clock phase acquisition operation is performed in the PLL circuit 112 of the data read section 100, in a head 101 as shown in FIG. 25, the acquisition operation is initiated (refer to time point t1) at a gap section (preamble section; refer to time points t1 to t3) recording a certain frequency on the disk and is completed (refer to time point t2) before the arrival of a data section (refer to time point t4 and thereafter) to enter the tracking operation (refer to time point t2 and thereafter).
It is known that a phase error computation circuit as shown in FIG. 26 can be adopted as the phase error computation circuit 107 upon achieving the phase acquisition operation.
Here, the phase error computation circuit 107 shown in FIG. 26 comprises a decision circuit 107a, three delay elements (D) 107b-1 to 107b-3, two multipliers 107c-1, 107c-2 and a subtracter 107d.
Here, the decision circuit 107a is a hysteresis type decision circuit for received signal (y.sub.n ; digital signal) quantized and equalized in the A/D converter 105 and the FIR filter 106, and for determining as binary digit (+1 or -1) its signal level (sample value) taking the previous (2 bits before) determination value Y.sub.n-2 as threshold. The decision circuit 107a outputs the determination result as Y.sub.n.
Delay elements 107b-1 to 107b-3 are designed to output the received signal delaying for 1 bit. Namely, the delay element 107b-1 is composed to output a signal y.sub.n-1 past by 1 bit when the signal y.sub.n is input from the FIR filter 106.
Similarly, the delay element 107b-2 is composed to output a signal Y.sub.n-1 by 1 bit past when the signal Y.sub.n is input from the decision circuit 107a thereto, while the delay element 107b-3 is made to output the signal Y.sub.n-1 past by 1 bit to the decision circuit 107a when the signal Y.sub.n-1 is input from the delay element 107b-2 thereto.
Now, the delay elements 107b-1, 107b-2, multipliers 107c-1, 107c-2 and the subtracter 107d compute the phase error E.sub..tau. by operation as shown by the following expression (1). EQU E.sub..tau. =y.sub.n-1 .multidot.Y.sub.n -y.sub.n .multidot.Y.sub.n-1( 1)
Suppose the signal input into the phase error computation circuit 107 when phase acquisition is initiated by the PLL circuit 112 is defined (y.sub.n-3, y.sub.n), the determination value (Y.sub.n-3, Y.sub.n-2) used for operations by the phase error computation circuit 107 is given as the initial setting value arbitrarily for example (+1, +1)!.
By using the phase error computation circuit 107 composed as mentioned above, in the PLL circuit 112, the phase acquisition is performed through the state transition on the time series as shown by the following FIG. 27(a) to FIG. 27(d). In this case also, (Y.sub.n-3, Y.sub.n-2)=(+1, +1) is given as the initial setting value.
First, as shown in FIG. 27(a), if the signal y.sub.n-1 (sample value 0.6) is input to the phase error computation circuit 107 upon the initiation of phase acquisition by the PLL circuit 112 (sample value of the signal y.sub.n following y.sub.n-1 is 1.2), the corresponding determination values from the decision circuit 107a will be Y.sub.n-1 =-1, Y.sub.n =+1 respectively. Consequently, the phase error E.sub..tau. as an operation result will be 1.8.
By this, in this VCO 110, the phase of the clock generated is controlled so that this phase error E.sub..tau. =1.8 becomes 0. In this case, the PLL circuit 112 acts in the direction to delay the phase. In other words, as the PLL circuit 112 determines Y.sub.n-1 and Y.sub.n respectively as -1 and +1, it operates so that these come to the inherent position.
Thereafter, passing through the state (the phase error E.sub..tau. =+1.2) where the sample value (Y.sub.n-1, y.sub.n)=(-0.2, 1.4) is input as shown in FIG. 27(b), the state where the phase error E.sub..tau. is 0 as shown in FIG. 27(c) is attained.
However, as the phase error computed by this phase error computation circuit 107 is integrated by a loop filter 109 of the following stage, the charge accumulated in capacitors composing this loop filter 109 can not be discharged immediately, resulting in the stage where the phase is delayed too much as shown in FIG. 27(d).
Consequently, in the state where the phase error E.sub..tau. =0 as shown in FIG. 27(c), the phase acquisition is not completed but the phase is being acquired continuously until attaining the state where the phase acquisition is completed (phase error E.sub..tau. =0) as shown in FIG. 27(e) passing through the state where the phase error E.sub..tau. is -1.2 as shown in FIG. 27(d).
Namely, while the sample value is at the position of (y.sub.b, y.sub.b-1) as shown in FIG. 28(a), the phase .tau. and the phase error E.sub..tau. will take the value corresponding to the point b shown in FIG. 28(b).
In this state, by operating the PLL circuit 112 as a feed back loop, the A/D conversion timing by the A/D converter 105 is controlled, the phase .tau. and the phase error E.sub..tau. of the sample value approach the point passing though the value corresponding to the point b', and the phase acquisition is completed. At this time, the sample value will settle into the position (y.sub.a-1, y.sub.a) shown in FIG. 28(a).
However, in the phase acquisition/tracking method by the PLL circuit adopting the phase error computation circuit as shown in FIG. 26, as the initial value of the determination value determined by the decision circuit 107a is given arbitrarily, the initialization is not made based on the input signal and there is a problem of requiring sometime, inconveniently, unnecessary time for phase acquisition.
To be more specific, while the point b indicating the phase error E.sub..tau. shown in FIG. 28(b) tries to approach the point a through the point b', considering the time necessary for the phase acquisition, the phase acquisition will be completed earlier if the PLL circuit 112 is operated so as to approach the point c where the phase acquisition is completed in the same way as the point a. Note that as the phase of the point c is integer "2" (position shifted by 720 degrees from the point a, position of phase "0"), it can be determined that the phase acquisition mode is completed.
Particularly in magnetic disk drives or the like, as the gap is recorded more previously than data is recorded for phase acquisition (refer to time points (t1) to (t3) in FIG. 25), when the phase acquisition time is longer, it takes a long time before reading out of data starts, and there is a problem of inconveniently deteriorating the response performance.
Moreover, if the gap section is made longer in response to a longer phase acquisition time, the unnecessary information should also be recorded, inconveniently decreasing the format efficiency.